Synchronous digital systems, including board level systems and chip level systems, rely on one or more clock signals to synchronize elements across the system. Typically, one or more clock signals are distributed across the system on one or more clock lines. However, due to various problems such as clock buffer delays, high capacitance of heavily loaded clock lines, and propagation delays, the edges of a clock signal in different parts of the system may not be synchronized. The time difference between a rising (or falling) edge in one part of the system with the corresponding rising (or falling) edge in another part of the system is referred to as “clock skew”.
Clock skew can cause digital systems to malfunction. For example, it is common for circuits in digital systems to have a first flip-flop output driving a second flip-flop input. With a synchronized clock signal on the clock input terminal of both flip-flops, the data in the first flip-flop is successfully clocked into the second flip-flop. However, if the active edge on the second flip-flop is delayed by clock skew, the second flip-flop might not capture the data from the first flip-flop before the first flip-flop changes state.
Delay lock loops are used in digital systems to minimize clock skew. Delay lock loops typically use delay elements to synchronize the active edges of a reference clock signal in one part of the system with a feedback clock signal from a second part of the system. FIG. 1 shows a block diagram of a conventional delay lock loop 100 coupled to logic circuits 190. Delay lock loop 100, which comprises a tuneable delay line 110 and a phase detector 120, receives a reference clock signal REF_CLK and drives an output clock signal O_CLK.
Tuneable delay line 110 delays reference clock signal REF_CLK by a variable propagation delay D before supplying output clock signal O_CLK. Thus, each clock edge of output clock signal O_CLK lags a corresponding clock edge of reference clock signal REF_CLK by propagation delay D. Phase detector 120 controls tuneable delay line 110, as described below.
Before output clock signal O_CLK reaches logic circuits 190, output clock signal O_CLK is skewed by clock skew 180. Clock skew 180 can be caused by delays in various clock buffers (not shown) or propagation delays on the clock signal line carrying output clock signal O_CLK (e.g., due to heavy loading on the clock signal line). To distinguish output clock signal O_CLK from the skewed version of output clock signal O_CLK, the skewed version is referred to as skewed clock signal S_CLK. Skewed clock signal S_CLK drives the clock input terminals (not shown) of the clocked circuits within logic circuits 190. Skewed clock signal S_CLK is also routed back to delay lock loop 100 on a feedback path 170. Typically, feedback path 170 is dedicated specifically to routing skewed clock signal S_CLK to delay lock loop 110. Therefore, any propagation delay on feedback path 170 is minimal and causes only negligible skewing.
Phase detector 120 controls delay line 110 to regulate propagation delay D. The actual control mechanism for delay lock loop 100 can differ. For example, in one version of delay lock loop 100, delay line 110 starts with a propagation delay D equal to minimum propagation delay D_MIN, after power-on or reset. Phase detector 110 then increases propagation delay D until reference clock signal REF_CLK is synchronized with skewed clock signal S_CLK. In another system, delay lock loop 100 starts with a propagation delay D equal to the average of minimum propagation delay D_MIN and maximum propagation delay D_MAX, after power-on or reset. Phase detector 120 then determines whether to increase or decrease (or neither) propagation delay D to synchronize reference clock signal REF_CLK with skewed clock signal S_CLK.
After synchronizing reference clock signal REF_CLK and skewed clock signal S_CLK, delay lock loop 100 monitors reference clock signal REF_CLK and skewed clock signal S_CLK and adjusts propagation delay D to maintain synchronization. A common reason for loss of synchronization is due to temperature changes in the system using delay lock loop 100. The changes in temperature also effects timing in tuneable delay line 110. Specifically, tuneable delay line 110 is generally formed by a series of buffer stages. FIG. 2 shows a typical tuneable delay line 200 having a multi-tap delay circuit 210 formed by plurality of buffer stages 210_1, 210_2, . . . 210_M, and a multiplexer 220. An input signal IN is received on the input terminal of buffer stage 210_1. The output terminal of each buffer stage 210_X is coupled to the input terminal of buffer stage 210_(X+1) as well as to an input terminal of multiplexer 220, where X is an integer between 1 and M−1, inclusive. The output terminal of buffer 210_M is coupled to an input terminal of multiplexer 210. For clarity, the output signal of a buffer stage 210_X is denoted as delayed output signal D_O[X], where X is an integer from 1 to M. Tap select signals TS selects one of the delayed output signals as output signal OUT of tuneable delay line 200.
In general each buffer stage is identical and provides a base delay B_D. Thus, delayed output signal D_O[X] is a copy of input signal IN delayed by X times base delay B_D. FIG. 3 illustrates a typical buffer stage 300. Buffer stage 300 includes a first inverter 310 and a second inverter 320 coupled in series. First inverter 310 includes a PMOS transistor 313 and an NMOS transistor 317 coupled in series between the positive supply voltage VCC and ground. Similarly, second inverter 320 includes a PMOS transistor 323 and an NMOS transistor 327 coupled in series between the positive supply voltage VCC and ground. The gate delays of transistors 313, 317, 323, and 327 provide base delay B_D. However, the gate delay of a transistor is dependent on the fabrication process. For example, factors such as implant and threshold voltage levels, which may vary somewhat between wafers, affect the gate delay of the transistors. Thus, base delay B_D may differ between different instances of tuneable delay line 200. Furthermore, the gate delay of a transistor is also dependent on temperature. In general, as temperature increases, gate delays (and thus base delay B_D) also increases. Similarly, as temperature decreases, gate delays (and thus base delay B_D) also decreases.
If base delay B_D becomes very small, maximum propagation delay D_MAX of tuneable delay line 110 (FIG. 1) may not be large enough compensate for clock skew 180. Conversely, if base delay B_D becomes too large, minimum propagation delay D_MIN of tuneable delay line 110 may not be small enough to compensate for clock skew 180. In addition if base delay B_D is large, delay lock loop 100 may introduce unacceptable jitter in output clock signal O_CLK. Hence, there is a need for circuit and method to adjust the propagation delay of a buffer stage to compensate for temperature and process variations.